added mx Project for the machine
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) 2024, STMicroelectronics - All Rights Reserved
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* Author: STM32CubeMX code generation for STMicroelectronics.
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*/
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/* For more information on Device Tree configuration, please refer to
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* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
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*/
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/dts-v1/;
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include <dt-bindings/soc/stm32mp15-etzpc.h>
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#include "stm32mp157.dtsi"
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#include "stm32mp15xd.dtsi"
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#include "stm32mp15xxac-pinctrl.dtsi"
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/* USER CODE BEGIN includes */
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#include <dt-bindings/gpio/stm32mp_gpio.h>
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#include <dt-bindings/power/stm32mp1-power.h>
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#include <dt-bindings/mfd/st,stpmic1.h>
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/* USER CODE END includes */
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/ {
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model = "STMicroelectronics STM32MP157D-DK1 STM32CubeMX board - openstlinux-6.1-yocto-mickledore-mp1-v23.06.21";
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compatible = "st,stm32mp157d-vrpmdv-mon-mx", "st,stm32mp157d-dk1", "st,stm32mp157";
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memory@c0000000 {
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device_type = "memory";
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reg = <0xc0000000 0x20000000>;
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/* USER CODE BEGIN memory */
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/* USER CODE END memory */
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* USER CODE BEGIN reserved-memory */
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mcuram2:mcuram2@10000000{
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compatible = "shared-dma-pool";
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reg = <0x10000000 0x40000>;
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no-map;
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};
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vdev0vring0:vdev0vring0@10040000{
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compatible = "shared-dma-pool";
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reg = <0x10040000 0x1000>;
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no-map;
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};
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vdev0vring1:vdev0vring1@10041000{
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compatible = "shared-dma-pool";
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reg = <0x10041000 0x1000>;
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no-map;
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};
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vdev0buffer:vdev0buffer@10042000{
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compatible = "shared-dma-pool";
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reg = <0x10042000 0x4000>;
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no-map;
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};
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mcuram:mcuram@30000000{
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compatible = "shared-dma-pool";
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reg = <0x30000000 0x40000>;
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no-map;
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};
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retram:retram@38000000{
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compatible = "shared-dma-pool";
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reg = <0x38000000 0x10000>;
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no-map;
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};
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gpu_reserved:gpu@d4000000{
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reg = <0xd4000000 0x4000000>;
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no-map;
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};
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/* USER CODE END reserved-memory */
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};
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/* USER CODE BEGIN root */
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aliases{
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serial0 = &uart4;
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serial1 = &usart3;
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serial2 = &uart7;
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};
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led{
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compatible = "gpio-leds";
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led-blue{
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label = "heartbeat";
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gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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default-state = "off";
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};
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};
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vin:vin{
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compatible = "regulator-fixed";
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regulator-name = "vin";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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chosen{
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stdout-path = "serial0:115200n8";
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};
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/* USER CODE END root */
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clocks {
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/* USER CODE BEGIN clocks */
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/* USER CODE END clocks */
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clk_hsi: clk-hsi {
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clock-frequency = <64000000>;
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/* USER CODE BEGIN clk_hsi */
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/* USER CODE END clk_hsi */
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};
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clk_lse: clk-lse {
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clock-frequency = <32768>;
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st,drive = < LSEDRV_MEDIUM_HIGH >;
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/* USER CODE BEGIN clk_lse */
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/* USER CODE END clk_lse */
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};
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clk_hse: clk-hse {
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clock-frequency = <24000000>;
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st,digbypass;
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/* USER CODE BEGIN clk_hse */
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/* USER CODE END clk_hse */
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};
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};
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}; /*root*/
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/*Warning: the configuration of the secured GPIOs should be added in (addons) User Section*/
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&pinctrl {
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/* USER CODE BEGIN pinctrl */
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uart4_pins_mx: uart4_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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};
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/* USER CODE END pinctrl */
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};
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&pinctrl_z {
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i2c4_pins_z_mx: i2c4_mx-0 {
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pins {
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pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
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<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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/* USER CODE BEGIN pinctrl_z */
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/* USER CODE END pinctrl_z */
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};
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&bsec{
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status = "okay";
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/* USER CODE BEGIN bsec */
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board_id:board_id@ec{
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reg = <0xec 0x4>;
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st,non-secure-otp;
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};
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huk_otp:huk-otp@f0{
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reg = <0xf0 0x10>;
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};
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/* USER CODE END bsec */
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};
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&etzpc{
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status = "okay";
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st,decprot = <
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/*"Non Secured" peripherals*/
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DECPROT(STM32MP1_ETZPC_ADC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_CEC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_I2C1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_SPI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_SAI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
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/*"NS_R S_W" peripherals*/
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DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
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DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
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/*"Secured" peripherals*/
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DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_S_RW, DECPROT_UNLOCK)
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DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
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/*Restriction: following IDs are not managed - please to use User-Section if needed:
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STM32MP1_ETZPC_SRAMx_ID STM32MP1_ETZPC_RETRAM_ID STM32MP1_ETZPC_BKPSRAM_ID*/
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/* USER CODE BEGIN etzpc_decprot */
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/*STM32CubeMX generates a basic and standard configuration for ETZPC.
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Additional device configurations can be added here if needed.
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"etzpc" node could be also overloaded in "addons" User-Section.*/
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/* USER CODE END etzpc_decprot */
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>;
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/* USER CODE BEGIN etzpc */
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/* USER CODE END etzpc */
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};
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&i2c4{
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_z_mx>;
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status = "okay";
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/* USER CODE BEGIN i2c4 */
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compatible = "st,stm32mp15-i2c-non-secure";
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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clock-frequency = <400000>;
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/delete-property/ dmas;
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/delete-property/ dma-names;
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pmic:stpmic@33{
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compatible = "st,stpmic1";
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reg = <0x33>;
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interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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regulators{
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compatible = "st,stpmic1-regulators";
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buck1-supply = <&vin>;
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buck2-supply = <&vin>;
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buck3-supply = <&vin>;
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buck4-supply = <&vin>;
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ldo1-supply = <&v3v3>;
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ldo2-supply = <&vin>;
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ldo3-supply = <&vdd_ddr>;
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ldo4-supply = <&vin>;
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ldo5-supply = <&vin>;
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ldo6-supply = <&v3v3>;
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vref_ddr-supply = <&vin>;
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boost-supply = <&vin>;
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pwr_sw1-supply = <&bst_out>;
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pwr_sw2-supply = <&bst_out>;
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vddcore:buck1{
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regulator-name = "vddcore";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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|
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lp-stop{
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regulator-on-in-suspend;
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||||
regulator-suspend-microvolt = <1200000>;
|
||||
};
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr:buck2{
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
|
||||
lp-stop{
|
||||
regulator-suspend-microvolt = <1350000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-suspend-microvolt = <1350000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd:buck3{
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
|
||||
lp-stop{
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
v3v3:buck4{
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
|
||||
lp-stop{
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
v1v8_audio:ldo1{
|
||||
regulator-name = "v1v8_audio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO1 0>;
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
v3v3_hdmi:ldo2{
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO2 0>;
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vtt_ddr:ldo3{
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
st,regulator-sink-source;
|
||||
|
||||
lp-stop{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_usb:ldo4{
|
||||
regulator-name = "vdd_usb";
|
||||
interrupts = <IT_CURLIM_LDO4 0>;
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda:ldo5{
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
interrupts = <IT_CURLIM_LDO5 0>;
|
||||
regulator-boot-on;
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
v1v2_hdmi:ldo6{
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO6 0>;
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vref_ddr:vref_ddr{
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
|
||||
lp-stop{
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-sr{
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
bst_out:boost{
|
||||
regulator-name = "bst_out";
|
||||
interrupts = <IT_OCP_BOOST 0>;
|
||||
};
|
||||
|
||||
vbus_otg:pwr_sw1{
|
||||
regulator-name = "vbus_otg";
|
||||
interrupts = <IT_OCP_OTG 0>;
|
||||
};
|
||||
|
||||
vbus_sw:pwr_sw2{
|
||||
regulator-name = "vbus_sw";
|
||||
interrupts = <IT_OCP_SWOUT 0>;
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
/* USER CODE END i2c4 */
|
||||
};
|
||||
|
||||
&iwdg1{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN iwdg1 */
|
||||
timeout-sec = <32>;
|
||||
/* USER CODE END iwdg1 */
|
||||
};
|
||||
|
||||
&pwr_regulators{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN pwr_regulators */
|
||||
system_suspend_supported_soc_modes = <
|
||||
STM32_PM_CSLEEP_RUN
|
||||
STM32_PM_CSTOP_ALLOW_LP_STOP
|
||||
STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR
|
||||
>;
|
||||
system_off_soc_mode = <STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF>;
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
/* USER CODE END pwr_regulators */
|
||||
};
|
||||
|
||||
&rcc{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN rcc */
|
||||
/* USER CODE END rcc */
|
||||
|
||||
st,clksrc = <
|
||||
CLK_CKPER_HSE
|
||||
CLK_ETH_PLL4P
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_STGEN_HSE
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_I2C46_HSI
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_RNG1_CSI
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
>;
|
||||
st,clkdiv = <
|
||||
DIV(DIV_MPU, 1)
|
||||
DIV(DIV_AXI, 0)
|
||||
DIV(DIV_MCU, 0)
|
||||
DIV(DIV_APB1, 1)
|
||||
DIV(DIV_APB2, 1)
|
||||
DIV(DIV_APB3, 1)
|
||||
DIV(DIV_APB4, 1)
|
||||
DIV(DIV_APB5, 2)
|
||||
DIV(DIV_RTC, 23)
|
||||
DIV(DIV_MCO1, 0)
|
||||
DIV(DIV_MCO2, 0)
|
||||
>;
|
||||
st,pll_vco {
|
||||
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
|
||||
src = < CLK_PLL12_HSE >;
|
||||
divmn = < 2 65 >;
|
||||
frac = < 0x1400 >;
|
||||
};
|
||||
pll3_vco_417Mhz: pll3-vco-417Mhz {
|
||||
src = < CLK_PLL3_HSE >;
|
||||
divmn = < 1 33 >;
|
||||
frac = < 0x1a04 >;
|
||||
};
|
||||
pll4_vco_594Mhz: pll4-vco-594Mhz {
|
||||
src = < CLK_PLL4_HSE >;
|
||||
divmn = < 3 98 >;
|
||||
};
|
||||
/* USER CODE BEGIN rcc_st-pll_vco */
|
||||
|
||||
pll4_vco_600Mhz:pll2-vco-600Mhz{
|
||||
src = <CLK_PLL4_HSE>;
|
||||
divmn = <3 98>;
|
||||
};
|
||||
/* USER CODE END rcc_st-pll_vco */
|
||||
};
|
||||
|
||||
pll2:st,pll@1 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <1>;
|
||||
|
||||
st,pll = < &pll2_cfg1 >;
|
||||
|
||||
pll2_cfg1: pll2_cfg1 {
|
||||
st,pll_vco = < &pll2_vco_1066Mhz >;
|
||||
st,pll_div_pqr = < 1 0 0 >;
|
||||
};
|
||||
/* USER CODE BEGIN pll2 */
|
||||
/* USER CODE END pll2 */
|
||||
};
|
||||
|
||||
pll3:st,pll@2 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <2>;
|
||||
|
||||
st,pll = < &pll3_cfg1 >;
|
||||
|
||||
pll3_cfg1: pll3_cfg1 {
|
||||
st,pll_vco = < &pll3_vco_417Mhz >;
|
||||
st,pll_div_pqr = < 1 16 36 >;
|
||||
};
|
||||
/* USER CODE BEGIN pll3 */
|
||||
/* USER CODE END pll3 */
|
||||
};
|
||||
|
||||
pll4:st,pll@3 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <3>;
|
||||
|
||||
st,pll = < &pll4_cfg1 >;
|
||||
|
||||
pll4_cfg1: pll4_cfg1 {
|
||||
st,pll_vco = < &pll4_vco_594Mhz >;
|
||||
st,pll_div_pqr = < 5 7 7 >;
|
||||
};
|
||||
/* USER CODE BEGIN pll4 */
|
||||
/* USER CODE END pll4 */
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&rng1{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN rng1 */
|
||||
/* USER CODE END rng1 */
|
||||
};
|
||||
|
||||
&rtc{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN rtc */
|
||||
/* USER CODE END rtc */
|
||||
};
|
||||
|
||||
&tamp{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN tamp */
|
||||
/* USER CODE END tamp */
|
||||
};
|
||||
|
||||
/* USER CODE BEGIN addons */
|
||||
|
||||
&gpu{
|
||||
contiguous-area = <&gpu_reserved>;
|
||||
};
|
||||
|
||||
&cpu0{
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&cpu1{
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&osc_calibration{
|
||||
|
||||
csi-calibration{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hsi-calibration{
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers15{
|
||||
status = "okay";
|
||||
|
||||
counter{
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&usbphyc_port0{
|
||||
phy-supply = <&vdd_usb>;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-fs-rftime-tuning;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <15>;
|
||||
st,trim-hs-impedance = <1>;
|
||||
st,tune-squelch-level = <3>;
|
||||
st,tune-hs-rx-offset = <2>;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
|
||||
&usbphyc_port1{
|
||||
phy-supply = <&vdd_usb>;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-fs-rftime-tuning;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <15>;
|
||||
st,trim-hs-impedance = <1>;
|
||||
st,tune-squelch-level = <3>;
|
||||
st,tune-hs-rx-offset = <2>;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
|
||||
|
||||
&uart4{
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_mx>;
|
||||
status = "okay";
|
||||
};
|
||||
/* USER CODE END addons */
|
||||
|
||||
@@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0-or-later BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
|
||||
* DDR type: DDR3 / DDR3L
|
||||
* DDR width: 16bits
|
||||
* DDR density: 4Gb
|
||||
* System frequency: 533000kHz
|
||||
* Relaxed Timing Mode: false
|
||||
* Address mapping type: RBC
|
||||
*
|
||||
* Save Date: 2024.04.29, save Time: 15:10:59
|
||||
*/
|
||||
|
||||
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz"
|
||||
#define DDR_MEM_SPEED 533000
|
||||
#define DDR_MEM_SIZE 0x20000000
|
||||
|
||||
#define DDR_MSTR 0x00041401
|
||||
#define DDR_MRCTRL0 0x00000010
|
||||
#define DDR_MRCTRL1 0x00000000
|
||||
#define DDR_DERATEEN 0x00000000
|
||||
#define DDR_DERATEINT 0x00800000
|
||||
#define DDR_PWRCTL 0x00000000
|
||||
#define DDR_PWRTMG 0x00400010
|
||||
#define DDR_HWLPCTL 0x00000000
|
||||
#define DDR_RFSHCTL0 0x00210000
|
||||
#define DDR_RFSHCTL3 0x00000000
|
||||
#define DDR_RFSHTMG 0x0081008B
|
||||
#define DDR_CRCPARCTL0 0x00000000
|
||||
#define DDR_DRAMTMG0 0x0F101B0F
|
||||
#define DDR_DRAMTMG1 0x000A041C
|
||||
#define DDR_DRAMTMG2 0x0608090F
|
||||
#define DDR_DRAMTMG3 0x0050400C
|
||||
#define DDR_DRAMTMG4 0x08040608
|
||||
#define DDR_DRAMTMG5 0x06060403
|
||||
#define DDR_DRAMTMG6 0x02020002
|
||||
#define DDR_DRAMTMG7 0x00000202
|
||||
#define DDR_DRAMTMG8 0x00001005
|
||||
#define DDR_DRAMTMG14 0x000000A0
|
||||
#define DDR_ZQCTL0 0xC2000040
|
||||
#define DDR_DFITMG0 0x02060105
|
||||
#define DDR_DFITMG1 0x00000202
|
||||
#define DDR_DFILPCFG0 0x07000000
|
||||
#define DDR_DFIUPD0 0xC0400003
|
||||
#define DDR_DFIUPD1 0x00000000
|
||||
#define DDR_DFIUPD2 0x00000000
|
||||
#define DDR_DFIPHYMSTR 0x00000000
|
||||
#define DDR_ODTCFG 0x06000600
|
||||
#define DDR_ODTMAP 0x00000001
|
||||
#define DDR_SCHED 0x00000C01
|
||||
#define DDR_SCHED1 0x00000000
|
||||
#define DDR_PERFHPR1 0x01000001
|
||||
#define DDR_PERFLPR1 0x08000200
|
||||
#define DDR_PERFWR1 0x08000400
|
||||
#define DDR_DBG0 0x00000000
|
||||
#define DDR_DBG1 0x00000000
|
||||
#define DDR_DBGCMD 0x00000000
|
||||
#define DDR_POISONCFG 0x00000000
|
||||
#define DDR_PCCFG 0x00000010
|
||||
#define DDR_PCFGR_0 0x00010000
|
||||
#define DDR_PCFGW_0 0x00000000
|
||||
#define DDR_PCFGQOS0_0 0x02100C03
|
||||
#define DDR_PCFGQOS1_0 0x00800100
|
||||
#define DDR_PCFGWQOS0_0 0x01100C03
|
||||
#define DDR_PCFGWQOS1_0 0x01000200
|
||||
#define DDR_PCFGR_1 0x00010000
|
||||
#define DDR_PCFGW_1 0x00000000
|
||||
#define DDR_PCFGQOS0_1 0x02100C03
|
||||
#define DDR_PCFGQOS1_1 0x00800040
|
||||
#define DDR_PCFGWQOS0_1 0x01100C03
|
||||
#define DDR_PCFGWQOS1_1 0x01000200
|
||||
#define DDR_ADDRMAP1 0x00070707
|
||||
#define DDR_ADDRMAP2 0x00000000
|
||||
#define DDR_ADDRMAP3 0x1F000000
|
||||
#define DDR_ADDRMAP4 0x00001F1F
|
||||
#define DDR_ADDRMAP5 0x06060606
|
||||
#define DDR_ADDRMAP6 0x0F060606
|
||||
#define DDR_ADDRMAP9 0x00000000
|
||||
#define DDR_ADDRMAP10 0x00000000
|
||||
#define DDR_ADDRMAP11 0x00000000
|
||||
#define DDR_PGCR 0x01442E02
|
||||
#define DDR_PTR0 0x0022AA5B
|
||||
#define DDR_PTR1 0x04841104
|
||||
#define DDR_PTR2 0x042DA068
|
||||
#define DDR_ACIOCR 0x10400812
|
||||
#define DDR_DXCCR 0x00000C40
|
||||
#define DDR_DSGCR 0xF200011F
|
||||
#define DDR_DCR 0x0000000B
|
||||
#define DDR_DTPR0 0x38D488D0
|
||||
#define DDR_DTPR1 0x098B00D8
|
||||
#define DDR_DTPR2 0x10023600
|
||||
#define DDR_MR0 0x00000840
|
||||
#define DDR_MR1 0x00000000
|
||||
#define DDR_MR2 0x00000208
|
||||
#define DDR_MR3 0x00000000
|
||||
#define DDR_ODTCR 0x00010000
|
||||
#define DDR_ZQ0CR1 0x00000038
|
||||
#define DDR_DX0GCR 0x0000CE81
|
||||
#define DDR_DX1GCR 0x0000CE81
|
||||
#define DDR_DX2GCR 0x0000CE80
|
||||
#define DDR_DX3GCR 0x0000CE80
|
||||
@@ -0,0 +1,12 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) 2024, STMicroelectronics - All Rights Reserved
|
||||
* Author: STM32CubeMX code generation for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/* For more information on Device Tree configuration, please refer to
|
||||
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
|
||||
*/
|
||||
|
||||
#define DDR_SIZE 0x20000000 /* 512MB */
|
||||
#include "stm32mp15-fw-config.dtsi"
|
||||
@@ -0,0 +1,480 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) 2024, STMicroelectronics - All Rights Reserved
|
||||
* Author: STM32CubeMX code generation for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/* For more information on Device Tree configuration, please refer to
|
||||
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp15-mx.dtsi"
|
||||
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15xd.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxac-pinctrl.dtsi"
|
||||
#include "stm32mp15-ddr.dtsi"
|
||||
|
||||
/* USER CODE BEGIN includes */
|
||||
/* USER CODE END includes */
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157D-DK1 STM32CubeMX board - openstlinux-6.1-yocto-mickledore-mp1-v23.06.21";
|
||||
compatible = "st,stm32mp157d-vrpmdv-mon-mx", "st,stm32mp157d-dk1", "st,stm32mp157";
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
|
||||
/* USER CODE BEGIN memory */
|
||||
/* USER CODE END memory */
|
||||
};
|
||||
|
||||
/* USER CODE BEGIN root */
|
||||
|
||||
vin:vin{
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vin";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
aliases{
|
||||
serial0 = &uart4;
|
||||
serial1 = &usart3;
|
||||
serial2 = &uart7;
|
||||
};
|
||||
|
||||
chosen{
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
/* USER CODE END root */
|
||||
|
||||
clocks {
|
||||
/* USER CODE BEGIN clocks */
|
||||
/* USER CODE END clocks */
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
clock-frequency = <64000000>;
|
||||
|
||||
/* USER CODE BEGIN clk_hsi */
|
||||
/* USER CODE END clk_hsi */
|
||||
};
|
||||
clk_lse: clk-lse {
|
||||
clock-frequency = <32768>;
|
||||
st,drive = < LSEDRV_MEDIUM_HIGH >;
|
||||
|
||||
/* USER CODE BEGIN clk_lse */
|
||||
/* USER CODE END clk_lse */
|
||||
};
|
||||
clk_hse: clk-hse {
|
||||
clock-frequency = <24000000>;
|
||||
st,digbypass;
|
||||
|
||||
/* USER CODE BEGIN clk_hse */
|
||||
/* USER CODE END clk_hse */
|
||||
};
|
||||
};
|
||||
|
||||
}; /*root*/
|
||||
|
||||
&pinctrl {
|
||||
sdmmc1_pins_mx: sdmmc1_mx-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_mx: uart4_mx-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* USER CODE BEGIN pinctrl */
|
||||
/* USER CODE END pinctrl */
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
i2c4_pins_z_mx: i2c4_mx-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
||||
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* USER CODE BEGIN pinctrl_z */
|
||||
/* USER CODE END pinctrl_z */
|
||||
};
|
||||
|
||||
&hash1{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN hash1 */
|
||||
/* USER CODE END hash1 */
|
||||
};
|
||||
|
||||
&i2c4{
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_z_mx>;
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN i2c4 */
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic:stpmic@33{
|
||||
compatible = "st,stpmic1";
|
||||
reg = <0x33>;
|
||||
interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
regulators{
|
||||
compatible = "st,stpmic1-regulators";
|
||||
buck1-supply = <&vin>;
|
||||
buck2-supply = <&vin>;
|
||||
buck3-supply = <&vin>;
|
||||
buck4-supply = <&vin>;
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo2-supply = <&vin>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo4-supply = <&vin>;
|
||||
ldo5-supply = <&vin>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
vref_ddr-supply = <&vin>;
|
||||
boost-supply = <&vin>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore:buck1{
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_ddr:buck2{
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd:buck3{
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
v3v3:buck4{
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
};
|
||||
|
||||
v1v8_audio:ldo1{
|
||||
regulator-name = "v1v8_audio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v3v3_hdmi:ldo2{
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vtt_ddr:ldo3{
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
st,regulator-sink-source;
|
||||
};
|
||||
|
||||
vdd_usb:ldo4{
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdda:ldo5{
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v1v2_hdmi:ldo6{
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_ddr:vref_ddr{
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
bst_out:boost{
|
||||
regulator-name = "bst_out";
|
||||
};
|
||||
|
||||
vbus_otg:pwr_sw1{
|
||||
regulator-name = "vbus_otg";
|
||||
};
|
||||
|
||||
vbus_sw:pwr_sw2{
|
||||
regulator-name = "vbus_sw";
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
/* USER CODE END i2c4 */
|
||||
};
|
||||
|
||||
&iwdg1{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN iwdg1 */
|
||||
timeout-sec = <32>;
|
||||
/* USER CODE END iwdg1 */
|
||||
};
|
||||
|
||||
&rcc{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN rcc */
|
||||
compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon";
|
||||
/* USER CODE END rcc */
|
||||
|
||||
st,clksrc = <
|
||||
CLK_CKPER_HSE
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_STGEN_HSE
|
||||
CLK_I2C46_HSI
|
||||
CLK_USBO_USBPHY
|
||||
CLK_UART24_HSI
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
>;
|
||||
st,clkdiv = <
|
||||
DIV(DIV_MPU, 1)
|
||||
DIV(DIV_AXI, 0)
|
||||
DIV(DIV_MCU, 0)
|
||||
DIV(DIV_APB1, 1)
|
||||
DIV(DIV_APB2, 1)
|
||||
DIV(DIV_APB3, 1)
|
||||
DIV(DIV_APB4, 1)
|
||||
DIV(DIV_APB5, 2)
|
||||
DIV(DIV_RTC, 23)
|
||||
DIV(DIV_MCO1, 0)
|
||||
DIV(DIV_MCO2, 0)
|
||||
>;
|
||||
st,pll_vco {
|
||||
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
|
||||
src = < CLK_PLL12_HSE >;
|
||||
divmn = < 2 65 >;
|
||||
frac = < 0x1400 >;
|
||||
};
|
||||
pll3_vco_417Mhz: pll3-vco-417Mhz {
|
||||
src = < CLK_PLL3_HSE >;
|
||||
divmn = < 1 33 >;
|
||||
frac = < 0x1a04 >;
|
||||
};
|
||||
pll4_vco_594Mhz: pll4-vco-594Mhz {
|
||||
src = < CLK_PLL4_HSE >;
|
||||
divmn = < 3 98 >;
|
||||
};
|
||||
/* USER CODE BEGIN rcc_st-pll_vco */
|
||||
|
||||
pll1_vco_1300Mhz:pll1-vco-1300Mhz{
|
||||
src = < CLK_PLL12_HSE >;
|
||||
divmn = < 2 80 >;
|
||||
frac = < 0x800 >;
|
||||
};
|
||||
|
||||
pll3_vco_417_8Mhz:pll3-vco-417_8Mhz{
|
||||
src = < CLK_PLL3_HSE >;
|
||||
divmn = < 1 33 >;
|
||||
frac = < 0x1a04 >;
|
||||
};
|
||||
/* USER CODE END rcc_st-pll_vco */
|
||||
};
|
||||
|
||||
pll2:st,pll@1 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <1>;
|
||||
|
||||
st,pll = < &pll2_cfg1 >;
|
||||
|
||||
pll2_cfg1: pll2_cfg1 {
|
||||
st,pll_vco = < &pll2_vco_1066Mhz >;
|
||||
st,pll_div_pqr = < 1 0 0 >;
|
||||
};
|
||||
/* USER CODE BEGIN pll2 */
|
||||
/* USER CODE END pll2 */
|
||||
};
|
||||
|
||||
pll3:st,pll@2 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <2>;
|
||||
|
||||
st,pll = < &pll3_cfg1 >;
|
||||
|
||||
pll3_cfg1: pll3_cfg1 {
|
||||
st,pll_vco = < &pll3_vco_417Mhz >;
|
||||
st,pll_div_pqr = < 1 16 36 >;
|
||||
};
|
||||
/* USER CODE BEGIN pll3 */
|
||||
/* USER CODE END pll3 */
|
||||
};
|
||||
|
||||
pll4:st,pll@3 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <3>;
|
||||
|
||||
st,pll = < &pll4_cfg1 >;
|
||||
|
||||
pll4_cfg1: pll4_cfg1 {
|
||||
st,pll_vco = < &pll4_vco_594Mhz >;
|
||||
st,pll_div_pqr = < 5 7 7 >;
|
||||
};
|
||||
/* USER CODE BEGIN pll4 */
|
||||
/* USER CODE END pll4 */
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&sdmmc1{
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_pins_mx>;
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN sdmmc1 */
|
||||
disable-wp;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
/* USER CODE END sdmmc1 */
|
||||
};
|
||||
|
||||
&uart4{
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_mx>;
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN uart4 */
|
||||
/* USER CODE END uart4 */
|
||||
};
|
||||
|
||||
&usbotg_hs{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN usbotg_hs */
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
usb-role-switch;
|
||||
/* USER CODE END usbotg_hs */
|
||||
};
|
||||
|
||||
&usbphyc{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN usbphyc */
|
||||
/* USER CODE END usbphyc */
|
||||
};
|
||||
|
||||
&usbphyc_port0{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN usbphyc_port0 */
|
||||
phy-supply = <&vdd_usb>;
|
||||
/* USER CODE END usbphyc_port0 */
|
||||
};
|
||||
|
||||
&usbphyc_port1{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN usbphyc_port1 */
|
||||
phy-supply = <&vdd_usb>;
|
||||
/* USER CODE END usbphyc_port1 */
|
||||
};
|
||||
|
||||
/* USER CODE BEGIN addons */
|
||||
|
||||
&bsec{
|
||||
|
||||
board_id:board_id@ec{
|
||||
reg = <0xec 0x4>;
|
||||
st,non-secure-otp;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0{
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&cpu1{
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&pwr_regulators{
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&rng1{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc{
|
||||
status = "okay";
|
||||
};
|
||||
/* USER CODE END addons */
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) 2024, STMicroelectronics - All Rights Reserved
|
||||
* Author: STM32CubeMX code generation for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/* For more information on Device Tree configuration, please refer to
|
||||
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
|
||||
*/
|
||||
|
||||
/* USER CODE BEGIN includes */
|
||||
#include "stm32mp15-scmi-u-boot.dtsi"
|
||||
/* USER CODE END includes */
|
||||
|
||||
/ {
|
||||
|
||||
/* USER CODE BEGIN root */
|
||||
|
||||
aliases{
|
||||
i2c3 = &i2c4;
|
||||
usb0 = &usbotg_hs;
|
||||
};
|
||||
|
||||
config{
|
||||
u-boot,boot-led = "heartbeat";
|
||||
u-boot,error-led = "error";
|
||||
u-boot,mmc-env-partition = "u-boot-env";
|
||||
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
|
||||
st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
};
|
||||
|
||||
led{
|
||||
|
||||
led-red{
|
||||
label = "error";
|
||||
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
/* USER CODE END root */
|
||||
|
||||
}; /*root*/
|
||||
|
||||
/* USER CODE BEGIN addons */
|
||||
|
||||
&uart4{
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&usbotg_hs{
|
||||
u-boot,force-b-session-valid;
|
||||
};
|
||||
|
||||
&uart4_pins_mx {
|
||||
u-boot,dm-pre-reloc;
|
||||
pins1 { /* UART4_RX */
|
||||
u-boot,dm-pre-reloc;
|
||||
/* pull-up on rx to avoid floating level */
|
||||
bias-pull-up;
|
||||
};
|
||||
pins2 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
/* USER CODE END addons */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user